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? semiconductor components industries, llc, 2013 december, 2013 ? rev. 1 1 publication order number: ncv7719/d ncv7719 octal half-bridge driver the ncv7719 octal is an eight channel half-bridge driver with protection features designed specifically for automotive and industrial motion control applications. the product has independent controls and diagnostics, and the drivers can be operated in forward, reverse, brake, and high impedance states. the device is controlled via a 16 bit spi interface and is daisy chain compatible. features ? low quiescent current sleep mode ? high?side and low?side drivers connected in half?bridge configurations ? integrated freewheeling protection (ls and hs) ? 0.55 a peak current ? r ds(on) = 1.0 (typ) ? 5 mhz spi communication ? 16 bit frame error detection ? daisy chain compatible with multiple of 8 bit devices ? compliance with 3.3 v and 5 v systems ? undervoltage and overvoltage lockout ? discriminated fault reporting ? over current protection ? over?temperature protection ? underload detection ? exposed pad package ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? this is a pb?free device typical applications ? automotive ? industrial ? dc motor management for hvac application marking diagram http://onsemi.com ssop24 nb ep case 940ak ncv7719 awlyywwg ncv7719 = specific device code a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package see detailed ordering and shipping information on page 24 o f this data sheet. ordering information
ncv7719 http://onsemi.com 2 figure 1. typical application ncv7719 out1 out2 low?side driver high?side driver ls hs out3 out4 ls hs ls hs out5 out6 ls hs ls hs out7 out8 ls hs low?side driver high?side driver protection: under load over temperature under?voltage over?voltage over current 16 ?bit serial data interface power on reset control logic so si sclk csb vcc en uc watchdog voltage regulator vs1 mra4003t3 13.2 v vs2 gnd
ncv7719 http://onsemi.com 3 figure 2. block diagram enable bias por spi 16 bit logic and latch fault reporting en vcc so si sclk csb vs1 drive 2 control logic wave shaping wave shaping low side driver high side driver fault ls under load overcurrent drive 1 out1 vs1 vs1 out2 vs2 vs overvoltage lockout vs1, vs2 drive 3 vs2 out3 drive 4 vs2 out4 drive 5 vs1 out5 drive 6 vs2 out6 thermal warning & shutdown vs drive 7 drive 8 out7 out8 vs1 vs1 vcc undervoltage lockout gnd gnd gnd gnd
ncv7719 http://onsemi.com 4 gnd out1 out5 out7 si vcc so en nc out6 out4 gnd gnd out2 out8 vs1 sclk csb reserved reserved vs2 nc out3 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 epad figure 3. pinout ? ssop24 pin function description the pin?out for the deca half?bridge in ssop24 package is shown in the table below. pin# ssop24 symbol description 1 gnd ground 2 out1 half?bridge output 1 3 out5 half?bridge output 5 4 out7 half?bridge output 7 5 si 16 bit serial communication input. 3.3v/5v (ttl) compatible ? internally pulled down. 6 vcc power supply input for logic. 7 so 16 bit serial communication output. 3.3v/5v compliant 8 en enable ? active high; wakes the device from sleep mode. 3.3v/5v (ttl) compatible ? internally pulled down. 9 nc no connection. this pin should be isolated from any traces or vias on the pcb board. 10 out6 half?bridge output 6 11 out4 half?bridge output 4 12 gnd ground 13 gnd ground 14 out3 half?bridge output 3 15 nc no connection. this pin should be isolated from any traces or vias on the pcb board. 16 vs2 power supply input for outputs 3, 4, 6, 9, and 10. this pin must be connected to vs1 externally. 17 reserved reserved for factory use ? this pin must be grounded. 18 reserved reserved for factory use ? this pin must be grounded. 19 csb chip select bar ? active low; enables serial communication operation. 3.3v/5v (ttl) compatible ? in- ternally pulled up. 20 sclk serial communication clock input. 3.3v/5v (ttl) compatible ? internally pulled down. 21 vs1 power supply input for outputs 1, 2, 5, 7, 8, and all pre?drivers. this pin must be connected to vs2 ex- ternally. 22 out8 half?bridge output 8 23 out2 half?bridge output 2 24 gnd ground epad exposed pad connect to gnd or leave unconnected.
ncv7719 http://onsemi.com 5 maximum ratings (voltages are with respect to gnd) rating symbol value unit vsx pin voltage (vs1, vs2) (dc) (ac), t < 500 ms, ivsx > ?2 a vsxdcmax vsxac ?0.3 to 40 ?1.0 v i/o pin voltage ( vcc, si, sclk, csb, so, en) viomax ?0.3 to 5.5 v outx pin voltage (dc) (ac) (ac), t< 500 ms, ioutx > ?1.1 a (ac), t< 500 ms, ioutx < 1 a voutxdc voutxac ?0.3 to 40 ?0.3 to 40 ?1.0 1.0 v outx pin current (out1, ..., out10) ioutximax ?2.0 to 2.0 a junction temperature range t j ?40 to 150 c storage temperature range tstr ?55 to 150 c peak reflow soldering temperature: pb?free 60 to 150 seconds at 217 c (note 1) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. see or download on semiconductor?s soldering and mounting techniques reference manual, solderrm/d. attributes characteristic symbol value unit short circuit reliability characterization aecq10x grade a ? esd capability human body model per aec?q100?002 vsx, outx all other pins machine model per aec?q100?003 vesd4k vesd2k vesd200 4.0 kv 2.0 kv 200 v moisture sensitivity level msl msl2 ? package thermal resistance ? still?air junction?to?ambient (note 2) (note 3) junction?to?board (note 2) (note 3) r ja r ja r jboard r jboard 54 26 22 14 c/w c/w c/w c/w 2. based on jesd51?3, 1.2 mm thick fr4, 2s0p pcb with 2 oz. copper and 18 thermal vias to 600 mm 2 spreader on bottom layer. 3. based on jesd51?7, 1.2 mm thick fr4, 1s2p pcb with 2 oz. copper and 18 thermal vias to 80x80 mm 1 oz. internal spreader plane s. recommended operating conditions parameter symbol min max unit digital supply input voltage vccop 3.15 5.25 v battery supply input voltage vsxop 5.5 28 v dc output current ixop ? 0.55 a junction temperature tjop ?40 125 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability.
ncv7719 http://onsemi.com 6 electrical characteristics (?40 c t j 150 c, 5.5 v vsx 40 v, 3.15 v v cc 5.25 v, en = v cc , unless otherwise specified.) characteristic symbol conditions min typ max unit power supplies supply current (vs1 + vs2) sleep mode iqvsx85 vs1 = vs2 = 13.2v, v cc = 0 v ?40 c to 85 c ? 1.0 2.5 a supply current (vs1 + vs2) active mode ivsop en = v cc , 5.5v < vsx < 28 v no load ? 2.5 5.0 ma supply current (vcc) sleep mode active mode iqv cc iv cc op csb = v cc , en = si = sclk = 0 v ?40 c to 85 c en = csb = v cc , si = sclk = 0v no load ? ? 1.0 1.5 2.5 3.0 a ma total sleep mode current i(vs1) + i(vs2) + i(vcc) iqtot sleep mode, ?40 c to 85 c vs1 = vs2 = 13.2 v, no load ? 2.0 5.0 a vcc power?on reset threshold v cc por v cc increasing ? 2.55 2.90 v vsx undervoltage detection threshold vsxuv vsx decreasing 3.5 4.1 4.5 v vsx undervoltage detection hysteresis vsxuhys 100 ? 450 mv vsx overvoltage detection threshold vsxov vsx increasing 30 36 40 v vsx overvoltage detection hysteresis vsxohys 1 2.5 4 v driver output characteristics output high r ds(on) (source) r dson hs iout = ?500 ma, vs = 13.2 v v cc = 3.15 v ? 1.0 2.25 output low r ds(on) (sink) r dson ls iout = 500 ma, vs =13.2 v v cc = 3.15 v ? 1.0 2.25 output path r ds(hsx+lsx) rdsonpath i out = |150| ma ? ? 4.0 source leakage current isrclkg13.2 isrclkg40 v cc = 5 v,out(1?10) = 0 v, ?40 c to 85 c; vsx = 13.2 v vsx = 40 v ?1.0 ?5.0 ? ? ? ? a a sink leakage current isnklkg13.2 isnklkg40 v cc = 5 v; out(1?10) = vsx = 13.2 v out(1?10) = vsx = 40 v ? ? ? ? 1.0 5.0 a a overcurrent shutdown threshold (source) isdsrc v cc = 5 v, vsx = 13.2 v ?2.0 ?1.2 ?0.8 a overcurrent shutdown threshold (sink) isdsnk v cc = 5 v, vsx = 13.2 v 0.8 1.2 2.0 a over current delay timer tdoc 10 25 50 s underload detection threshold (low side) iuldls v cc = 5 v, vsx = 13.2 v 2.0 11 20 ma underload detection delay time tduld v cc = 5 v, vsx = 13.2 v 200 350 600 s body diode forward voltage ibdfwd if = 500 ma ? 0.9 1.3 v driver output switching characteristics high side turn on time thson vs = 13.2 v, r load = 39 ? 7.5 13 s high side turn off time thsoff vs = 13.2 v, r load = 39 ? 3.0 6.0 s low side turn on time tlson vs = 13.2 v, r load = 39 ? 6.5 13 s low side turn off time tlsoff vs = 13.2 v, r load = 39 ? 2.0 5.0 s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. not production tested. 5. this is the minimum time the user must wait between spi commands. 6. this is the minimum time the user must wait between consecutive srr requests.
ncv7719 http://onsemi.com 7 electrical characteristics (?40 c t j 150 c, 5.5 v vsx 40 v, 3.15 v v cc 5.25 v, en = v cc , unless otherwise specified.) characteristic unit max typ min conditions symbol driver output switching characteristics high side rise time thstr vs = 13.2 v, r load = 39 ? 4.0 8.0 s high side fall time thstf vs = 13.2 v, r load = 39 ?? 2.0 4.0 s low side rise time tlstr vs = 13.2 v, r load = 39 ? 1.0 3.0 s low side fall time tlstf vs = 13.2 v, r load = 39 ? 1.0 3.0 s high side off to low side on non?overlap time thsofflson vs = 13.2 v, r load = 39 1.5 ? ? s low side off to high side on non?overlap time tlsoffhson vs = 13.2 v, r load = 39 1.5 ? ? s thermal response thermal warning twr (note 4) 120 140 170 c thermal warning hysteresis twhy (note 4) ? 20 ? c thermal shutdown ts d (note 4) 150 175 200 c thermal shutdown hysteresis tsdhy (note 4) ? 20 ? c logic inputs ? en, si, sclk, csb input threshold high low vthinh vthinl 2.0 ? ? ? ? 0.6 v v input hysteresis ? si, sclk, csb vthinhys 50 150 300 mv input hysteresis ? en vthenhys 150 400 800 mv pull?down resistance ? en, si, sclk rpdx en = si = sclk = v cc 50 125 200 k pull?up resistance ? csb rpucsb csb = 0 v 50 125 250 k input capacitance cinx (note 4) ? ? 15 pf logic output ? so output high vsoh isource = ?1 ma v cc ? 0.6 ? ? v output low vsol isink = 1.6 ma ? ? 0.4 v tri?state leakage itristlkg csb = 5 v ?5 ? 5 a tri?state output capacitance itristcout csb = v cc , 0 v < v cc < 5.25 v (note 4) ? ? 15 pf serial peripheral interface characteristic symbol conditions timing charts # min typ max unit sclk frequency fclk ? ? ? 5.0 mhz sclk clock period tpclk v cc = 5 v v cc = 3.3 v ? 200 500 ? ? ? ? ns sclk high time tclkh 1 85 ? ? ns sclk low time tclkl 2 85 ? ? ns sclk setup time tclksup 3, 4 85 ? ? ns si setup time tsisup 11 50 ? ? ns si hold time tsih 12 50 ? ? ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. not production tested. 5. this is the minimum time the user must wait between spi commands. 6. this is the minimum time the user must wait between consecutive srr requests.
ncv7719 http://onsemi.com 8 electrical characteristics (?40 c t j 150 c, 5.5 v vsx 40 v, 3.15 v v cc 5.25 v, en = v cc , unless otherwise specified.) serial peripheral interface characteristic unit max typ min timing charts # conditions symbol csb setup time tcsbsup 5, 6 100 ? ? ns csb high time tcsbh (note 5) 7 5.0 ? ? s so enable after csb falling edge tenso 8 ? ? 200 ns so disable after csb rising edge tdisso 9 ? ? 200 ns so rise/fall time tsor/f cload = 40 pf (note 4) ? ? 10 25 ns so valid time tsov cload = 40 pf (note 4) sclk to so 50% 10 ? 20 50 ns en low valid time tenl v cc = 5v; en h l 50% to outx turning off 50% ? 10 ? ? s en high to spi valid tenhspiv ? ? ? 100 s srr delay between consecutive frames tsrr (note 6) ? 150 ? ? s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. not production tested. 5. this is the minimum time the user must wait between spi commands. 6. this is the minimum time the user must wait between consecutive srr requests.
ncv7719 http://onsemi.com 9 characteristic timing diagrams ls turn off hs turn on csb tlsoff tlstr thstr tlsoffhson thson hs turn off ls turn on csb thsoff tlson tlstf thstf thsofflson 10% 10% 10% 10% 90% 90% 90% 90% 90% 90% figure 4. detailed driver timing
ncv7719 http://onsemi.com 10 10 si sclk so 11 12 csb sclk 3 1 2 5 4 7 6 csb so 8 9 figure 5. detailed spi timing
ncv7719 http://onsemi.com 11 typical performance curves figure 6. iqtot vs. temperature temperature ( c) sleep mode current ( a) 150 ?30 ?50 6.0 ?10 10 30 50 70 90 110 130 5.0 4.0 3.0 2.0 1.0 0 v cc = 5.25 v v cc = 5 v v cc = 3.15 v vsx = 13.2 v figure 7. i(v cc ) active mode vs. v(v cc ) v cc voltage (v) acitve mode vcc current (ma) 5.5 3.0 2.3 2.3 2.2 2.2 2.1 2.1 2.0 3.5 4.0 4.5 5.0 vsx = 13.2 v 150 c ?40 c 125 c 25 c figure 8. r ds(on) vs. temperature temperature ( c) r ds(on) ( ) 150 ?50 2.0 0 50 100 1.8 1.6 1.4 1.2 1.0 0.8 0.6 vsx = 13.2 v hsx lsx i f = 0.5 a lsx hsx figure 9. body diode voltage vs. temperature temperature ( c) body diode forward voltage (v) 1.2 1.1 1.0 0.9 0.8 150 ?50 0 50 100 figure 10. over current vs. temperature temperature ( c) i sdsrc , i sdsnk , overcurrent (a) 150 ?50 2.0 0 50 100 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 lsx hsx vs = 13.2 v, v cc = 5.0 v i srclkg , i snklkg , leakage current ( a) 0.20 0 ?0.20 ?0.40 ?0.60 ?0.80 ?1.00 ?1.20 ?1.40 temperature ( c) 150 ?50 0 50 100 figure 11. leakage current vs. temperature lsx hsx vsx = 13.2 v
ncv7719 http://onsemi.com 12 detailed operating description general overview the ncv7719 is comprised of twenty power drivers (10 pmos high?side and 10 nmos low?side). the drivers are arranged as ten half?bridge output channels, allowing for five independent full?bridge configured loads. output control and status reporting is handled via the spi (serial peripheral interface) communications port. each output is characterized for a maximum 0.55 a dc load and has a maximum 2.0 a surge capability (at vsx = 13.2 v). maximum allowable junction temperature is 150 c and may constrain the maximum load current and/or limit the number of drivers active at once. an active?high enable function (en) allows global control of the outputs and provides a low quiescent current sleep mode when the device is not being utilized. an internal pull?down resistor is provided on the input to ensure the device enters sleep mode if the input signal is lost. when en is asserted, the v cc por cycle will proceed and bring the device into normal operation. the device configuration registers can then be programmed via spi. de?asserting en clears all registers (no configuration or status data is stored), resets the drivers, and enters sleep mode. spi communication 16?bit full duplex spi communication has been implemented for device configuration, driver control, and reading the status data. in addition to the 16?bit status data, a pseudo?bit (pre_15) can also be retrieved from the so output. the device must be enabled (en = h) for spi communication. the spi inputs are ttl compatible and the so output high level is defined by the applied v cc . the active?low csb input has a pull?up resistor and the remaining inputs have pull?down resistors to bias them to known states when the spi is not active. the latched thermal shutdown (tsd) status bit pre_15 is available on so until the first rising sclk edge after csb goes low. the following conditions must be met for a valid tsd read to be captured: 1. sclk and si are low before the csb cycle; 2. csb transitions from high to low; 3. csb setup time (tcsbsup: figure 5, #5) is satisfied. figure 12 shows the spi communication frame format, and tables 1 and 2 define the command input and diagnostic status output bits. figure 12. spi communication frame format pre_15 pseudo?bit ocs psf uld b[12:7] hbst[6:1] b[8:7] hbst[8:7] b[6:1] hbcr[6:1] b[2:1] hbcr[8:7] tsd tw srr hbsel uldsc b[12:7] hben[6:1] b[8:7] hben[8:7] b[6:1] hbcnf[6:1] b[2:1] hbcnf[8:7] 15 14 13 0 ovlo csb si sclk so communication is implemented as follows and is also illustrated in figures 12 and 14: 1. si and sclk are set to low before the csb cycle. 2. csb goes low to begin a serial data frame; pseudo?bit pre_15 is immediately available at so. 3. si data is shifted in on every rising edge of sclk, starting with the most significant bit (msb), srr. 4. si data is recognized on every falling edge of the sclk. 5. current so data is simultaneously shifted out on every rising edge of sclk, starting with the msb (ocs). 6. csb goes high to end the frame and so becomes tri?state. 7. the last 16 bits clocked into si are transferred to the device?s data register if no frame error is detected, otherwise the entire frame is ignored and the previous input data is preserved.
ncv7719 http://onsemi.com 13 table 1. spi command input definitions channels 8 ? 7 (input bit # 14 = 1) bit# name function status* scope 15 srr status register reset** 1 = reset status reset per hbsel 14 hbsel channel group select 1 = hb [10:7] 1 = hb [10:7] | 0 = hb [6:1] 13 uldsc underload shutdown 1 = enabled enabled per hbsel ; per half?bridge operation 12 x not used ? ? 11 10 9 8 hben8 enable half?bridge 8 0 = hi?z 1 = enabled per half?bridge 7 hben7 enable half?bridge 7 6 x not used ? ? 5 4 3 2 hbcnf8 configure half?bridge 8 0 = ls on, hs off 1 = ls off, hs on per half?bridge 1 hbcnf7 configure half?bridge 7 0 ovlo vsx overvoltage lockout 1 = enabled global lockout channels 6 ? 1 (input bit # 14 = 0) bit# name function status* scope 15 srr status register reset** 1 = reset status reset per hbsel 14 hbsel channel group select 0 = hb [6:1] 1 = hb [10:7] | 0 = hb [6:1] 13 uldsc underload shutdown 1 = enabled enabled per hbsel ; per half?bridge operation 12 hben6 enable half?bridge 6 0 = hi?z 1 = enabled per half?bridge 11 hben5 enable half?bridge 5 10 hben4 enable half?bridge 4 9 hben3 enable half?bridge 3 8 hben2 enable half?bridge 2 7 hben1 enable half?bridge 1 6 hbcnf6 configure half?bridge 6 0 = ls on, hs off 1 = ls off, hs on per half?bridge 5 hbcnf5 configure half?bridge 5 4 hbcnf4 configure half?bridge 4 3 hbcnf3 configure half?bridge 3 2 hbcnf2 configure half?bridge 2 1 hbcnf1 configure half?bridge 1 0 ovlo vsx overvoltage lockout 1 = enabled global lockout *all command input bits are set to 0 at v cc power?on reset. **latched faults are cleared and outputs can be re?programmed if no fault exists after srr asserted.
ncv7719 http://onsemi.com 14 table 2. spi status output definitions channels 8 ? 7 (input bit # 14 = 1) bit# name function status* scope pre_15 tsd latched thermal shutdown 1 = fault global notification; per half?bridge operation 15 ocs latched overcurrent shutdown 1 = fault notification per hbsel ; per half?bridge operation 14 psf vs1 and/or vs2 undervoltage or overvoltage 1 = fault global notification and global operation 13 uld underload detect 1 = fault notification per hbsel ; per half?bridge operation 12 x not used (hard coded to zero) ? 11 10 9 8 hbst8 half?bridge 8 output status 0 = hi?z 1 = enabled per half?bridge 7 hbst7 half?bridge 7 output status 6 x not used (hard coded to zero) ? 5 4 3 2 hbcr8 half?bridge 8 config status 0 = ls on, hs off 1 = ls off, hs on** per half?bridge 1 hbcr7 half?bridge 7 config status 0 tw thermal warning 1 = fault global notification; per half?bridge operation *all status output bits are set to 0 at vcc power?on reset (por). **hbcrx is forced to 0 when hbstx = 0 via por, spi, or fault.
ncv7719 http://onsemi.com 15 table 2. spi status output definitions channels 6 ? 1 (if previous input bit # 14 = 0) bit# name function status* scope pre_15 tsd latched thermal shutdown 1 = fault global notification; per half?bridge operation 15 ocs latched overcurrent shutdown 1 = fault notification per hbsel ; per half?bridge operation 14 psf vs1 and/or vs2 undervoltage or overvoltage 1 = fault global notification and global operation 13 uld underload detect 1 = fault notification per hbsel ; per half?bridge operation 12 hbst6 half?bridge 6 output status 0 = hi?z 1 = enabled per half?bridge 11 hbst5 half?bridge 5 output status 10 hbst4 half?bridge 4 output status 9 hbst3 half?bridge 3 output status 8 hbst2 half?bridge 2 output status 7 hbst1 half?bridge 1 output status 6 hbcr6 half?bridge 6 config status 0 = ls on, hs off 1 = ls off, hs on** per half?bridge 5 hbcr5 half?bridge 5 config status 4 hbcr4 half?bridge 4 config status 3 hbcr3 half?bridge 3 config status 2 hbcr2 half?bridge 2 config status 1 hbcr1 half?bridge 1 config status 0 tw thermal warning 1 = fault global notification; per half?bridge operation *all status output bits are set to 0 at vcc power?on reset (por). **hbcrx is forced to 0 when hbstx = 0 via por, spi, or fault. frame error detection the ncv7719 employs frame error detection to help ensure input data integrity . sclk is compared to an n x 8 bit counter and a valid frame (csb h?l?h cycle) has integer multiples of 8 sclk cycles. for the first 16 bits shifted into si, sclk is compared to a modulo16 counter (n = 2), and sclk is compared to a modulo 8 counter (n = 1, 2, ...m) thereafter. this variable modulus facilitates daisy chain operation with devices using different word lengths. the last 16 bits clocked into si are transferred to the ncv7719?s data register if no frame error is detected, otherwise the entire frame is ignored and the previous input data is preserved. daisy chain operation daisy chain operation is possible with multiple 16?bit and 8?bit devices that have a compatible spi protocol. the clock phase and clock polarity with respect to the data for all the devices in the chain must be the same as the ncv7719. csb and sclk are parallel connected to every device in the chain while so and si are series connected between each device. the master?s mosi is connected to the si of the first device and the first device?s so is connected to the next device?s si. the so of the final device in the chain is connected to the master?s miso. the hardware configuration for the ncv7719 daisy chained with an 8? bit spi device is shown in figure 13. a 24?bit frame made of 16?bit word ?a ? and 8?bit word ?b? is sent from the master. command word b is sent first followed by word a. the master simultaneously receives status word b first followed by word a. the progression of data from the mcu through the sequential devices is illustrated in figure 14. compliance with the illustrated frame format is required for proper daisy chain operation. situations should be avoided where an incorrect multiple of 8 bits is sent to the devices, but the frame length does not cause a frame error in the devices. for example, the word order could be inadvertently interleaved or reversed. invalid data is accepted by the ncv7719 in such scenarios and possibly by other devices in the chain, depending on their frame error implementation. data is received as a command by the device at the beginning of the chain, but the device at the end of the chain may receive status data from the preceding device as a command.
ncv7719 http://onsemi.com 16 figure 13. daisy chain configuration ncv7719 16?bit device csb sclk si so 8?bit device csb sclk si so device b cmd [x, n] = command word to device ?x?, length ?n? sta [x, n] = status word from device ?x?, length ?n? device a cmd [b, 8] + cmd [a, 16] sta [a, 16] + cmd [b, 8] sta [b, 8] + sta [a, 16] mcu csb sclk miso master mosi sclk csb si 7 6 1 0 15 word b ? 8 bits word a ? 16 bits 24bit frame modulo 16 counter begins on the first rising sclk edge after csb goes low. si data is recognized on the falling sclk edge . so data is shifted out on the rising sclk edge. tsd so msb msb lsb lsb msb msb 0 lsb lsb 8 7 modulo 16 counter ends ? 16 bit word length valid. modulo 8 counter begins on the next rising sclk edge. modulo 8 counter ends ? 8 bit word length valid. valid n*8 bit frame. figure 14. daisy chain ? 24 bit frame format tsd bit in daisy chain operation the so path is designed to allow tsd status retrieval in a daisy chain configuration using ncv7719 or other devices with identical spi functionality. the tsd status bit is or?d with si and then multiplexed with the device?s usual status data (figure 15). csb is held high and si and sclk are held low by the master before the start of the spi frame. tsd status is immediately available as bit pre_15 at so (so = tsd) when csb goes low to begin the frame. the usual status data (so = sta) becomes available after the first rising sclk edge. the tsd status automatically propagates through the chain from the so output of the previous device to the si input of the next. this is shown in figures 16 and 17, first without a tsd fault in either device (figure 16), and then subsequently with a latched tsd fault (tsd = 1) in device ?a? propagating through to device ?b? (figure 17). since the tsd status of any device propagates automatically through the entire chain, it is not possible to determine which device (or devices) has a fault (tsd = 1). the usual status data from each device will need to be examined to determine where a fault (or faults) may exist.
ncv7719 http://onsemi.com 17 m u x so si tsd spi si sel so figure 15. tsd spi link ncv7718/19/20 ncv7719 csb sclk si so csb sclk si so device b device a 0 1 0 mcu csb sclk miso master mosi 0 z 0 z 0 no tsd no tsd figure 16. daisy chain without tsd fault ncv7718/19/20 ncv7719 csb sclk si so csb sclk si so device b device a 0 1 0 mcu csb sclk miso master mosi 0 z 1 z 1 latched tsd no tsd figure 17. daisy chain with tsd fault power up/down control the v cc supply input powers the device?s logic core. a v cc power?on reset (por) function provides controlled power?up/down. v cc por initializes the command input and status output registers to their default states (0x00), and ensures that the bridge output and so drivers maintain hi?z as power is applied. spi communication and normal device operation can proceed once v cc rises above the por threshold. the vs1 and vs2 supply inputs power their respective output drivers (refer to figure 2 and the pin function description). the vsx inputs are monitored to ensure that the supply stays within the recommended operating range. if the vsx supply moves into either of the vs undervoltage or overvoltage regions, the output drivers are switched to hi?z but command and status data is preserved. driver control the ncv7719 has the flexibility to control each half?bridge driver channel via spi. actual driver output state is determined by the command input and the current fault status bits as shown in figure 18 and table 3. the channels are divided into two groups and each group is selected by the hbsel input bit (see t able 1 ). high?side (hsx) and low?side (lsx) drivers of the same channel cannot be active at the same time, and non?overlap delays are imposed when switching between hsx and lsx drivers in the same channel. this control design thus prevents current shoot?through. after the device has powered up and the drivers are allowed to turn on, the drivers remain on until commanded off via spi or until a fault condition occurs.
ncv7719 http://onsemi.com 18 fault control hbcnfx hsx lsx vs hbenx hbstx outx hbcrx ocs tsd uld spi ?uldsc spi ?ovlo psf ?vsov q s r psf ?vsuv latch srr (reset dominant) gnd spi figure 18. simplified half?bridge control logic table 3. output state vs. command and status command status outx hbenx hbcnfx hbstx hbcrx x x 0 0 z 0 x 0 0 z 1 0 1 0 gnd 1 1 1 1 vs
ncv7719 http://onsemi.com 19 diagnostics, protections, status reporting and reset overview the ncv7719 employs diagnostics designed to prevent destructive overstress during a fault condition. diagnostics are classified as either supervisory or protection functions (table 4) . supervisory functions provide status information about device conditions. protection functions provide status information and activate fault management behaviors. diagnostics resulting in output shutdown and latched status may depend on a qualifier and may require user intervention for output recovery and status memory clear. diagnostics resulting in output lockout and non?latched status (vsov or vsuv) may recover and clear automatically. output configurations can be changed during output lockout. outputs assume the new configurations or resume the previous configurations when an auto?recover fault is resolved. table 5 shows output states during faults and output recovery modes, and table 6 shows the status memory and memory clear modes. table 4. diagnostic classes and functions name class function tsd protection thermal shutdown ocs protection overcurrent shutdown psf supervisory under/overvoltage lockout uld protection underload shutdown hbstx supervisory half?bridge x output status hbcrx supervisory half?bridge x config status tw supervisory thermal warning table 5. output state vs. fault and output recovery fault qualifier outx state outx recovery tsd ? z send srr ocs ? z send srr psf ? vsov ovlo = 1 z y n | y n+1 auto* ovlo = 0 unaffected ? psf ? vsuv ? z y n | y n+1 auto* uld uldsc = 1 z send srr uldsc = 0 unaffected ? tw ? unaffected ? *outx returns to its previous state (y n ) or new state (yn+1) if fault is removed. table 6. status memory vs. fault and memory clear fault qualifier status memory memory clear tsd ? latched send srr ocs ? latched send srr psf ? vsov ovlo = x non?latched auto* psf ? vsuv ? non?latched auto* uld uldsc = x latched send srr tw ? non?latched auto* *status memory returns to its no?fault state if fault is removed.
ncv7719 http://onsemi.com 20 status information retrieval current status information as selected by hbsel is retrieved during each spi frame. to preserve device configuration and output states, the previous si data pattern must be sent during the status retrieval frame. status information is prevented from being updated during a spi frame but new status becomes available after csb goes high at the end of the frame provided the frame did not contain an srr request. for certain device faults, it may not be possible to determine which channel (or channels) has a particular fault (or faults) since notification may be via a single global status bit. the complete status data from all channels may need to be examined to determine where a fault may exist. status register reset ? srr sending srr = 1 clears status memory and re?activates faulted outputs for channels as selected by hbsel. the previous si data pattern must be sent with srr to preserve device configuration and output states. srr takes effect at the rising edge of csb and a timer (tsrr) is started. tsrr is the minimum time the user must wait between consecutive srr requests. if a fault is still present when srr is sent, protection can be re?engaged and shutdown can recur. the device can also be reset by toggling the en pin or by vcc power?on reset. diagnostics details the following sections describe the individual diagnostics and some behaviors. in each description and illustration, a spi frame is assumed to always be valid and the si data pattern sent for hbcnfx and hbenx is the same as the previous frame. actual results can depend on asynchronous fault events and spi clock frequency and frame rate. undervoltage lockout global notification, global operation undervoltage detection and lockout control is provided by monitoring the vs1, vs2 and v cc supply inputs. undervoltage hysteresis is provided to ensure clean detection transitions. undervoltage timing is shown in figure 19. undervoltage at either vsx input turns off all outputs and sets the power supply fail (psf) status bit. the outputs return to their previously programmed state and the psf status bit is cleared when vsx rises above the hysteresis voltage level. spi is available and programmed output enable and configuration states are maintained if proper v cc is present during vsx undervoltage. v cc undervoltage turns all outputs off and clears the command input and status output registers. outx ls ? outx ls ? x no fault outx ls psf all z outx ls no fault 0x00 all z vsx vcc ? outx hs outx hs vsuv vccuv no fault psf no fault 0x00 outx vs no fault outx hs no fault t outx gnd outx gnd si status output state so z figure 19. undervoltage timing
ncv7719 http://onsemi.com 21 overvoltage lockout global notification, global operation overvoltage detection and lockout control is provided by monitoring the vs1 and vs2 supply inputs. overvoltage hysteresis is provided to ensure clean detection transitions. overvoltage timing is shown in figure 20. overvoltage at either vsx input turns off all outputs if the overvoltage lockout input bit is set (ovlo = 1, hbsel = x), and sets the power supply fail (psf) status bit (see tables 5 and 6). the outputs return to their previously programmed state and the psf status bit is cleared when vsx falls below the hysteresis voltage level. to reduce stress, it is recommended to operate the device with ovlo bit asserted to ensure that the drivers turn off during a load dump scenario. ? ? outx on psf all z vsx vsov psf no fault no fault t si status output state so outx on ovlo=0 x outx on no fault no fault outx on outx on ovlo=1 no fault vsov psf psf outx on outx on no fault outx off no fault outx z figure 20. overvoltage timing overcurrent shutdown notification per hbsel, per half?bridge operation overcurrent detection and shutdown control is provided by monitoring each hs and ls driver. overcurrent timing is shown in figure 21. overcurrent in either driver starts a channel?s overcurrent delay timer. if overcurrent exists after the delay, both drivers are latched off and the overcurrent (ocs) status bit is set. the ocs bit is cleared and channels are re?activated by sending srr = 1. the channel group select (hbsel) input bit determines which channels are affected by srr. a persistent overcurrent cause should be resolved prior to re?activation to avoid repetitive stress on the drivers. extended exposure to stress may affect device reliability. outx on ocs isdsxx t si status output state so outx on srr=0 outx on no fault outx on srr=1 outx on outx z output current outx on no fault no fault tdoc ocs outx z tdoc outx on no fault no fault outx on ocs ocs ocs figure 21. overcurrent timing
ncv7719 http://onsemi.com 22 underload shutdown notification per hbsel, shutdown per hbsel underload detection and shutdown control is provided by monitoring each ls driver. underload timing is shown in figure 22. underload at a ls driver starts the global underload delay timer. if underload occurs in another channel after the global timer has been started, the delay for any subsequent underload will be the remainder of the timer. the timer runs continuously with a persistent underload condition. if underload exists after the delay and if the underload shutdown (uldsc) command bit is set, both hs and ls drivers are latched off and the underload (uld) status bit is set; otherwise the drivers remain on and the uld bit is set (see t able 5 and 6). the uld bit is cleared and channels are re?activated by sending srr = 1. the channel group select (hbsel) input bit determines which channels are affected by srr and also determines which half?bridges are latched off via the uldsc command bit (see table 1). underload may result from a fault (e.g. open?load) condition or normal circuit behavior (e.g. l/r tau). in motor applications it is often desirable to actively brake the motor by turning on both hs or ls drivers in two half?bridge channels. if the configuration is two ls drivers (ls brake), an underload will result as the motor current decays normally. utilizing hs brake instead will avoid underload notification. si status output state so output current t lsx on uldsc=0 lsx on no fault lsx on srr=1 no fault no fault uld outx on uld uld lsx on uldsc=1 uld lsx on srr=1 lsx on outx gnd tduld tduld outx z outx gnd no fault no fault tduld figure 22. underload timing no fault uld iuldls
ncv7719 http://onsemi.com 23 thermal warning and thermal shutdown global notification, per half?bridge operation thermal warning (tw) and thermal shutdown (tsd) detection and control are provided for each half?bridge by monitoring the driver pair?s thermal sensor. thermal hysteresis is provided for each of the warning and shutdown functions to ensure clean detection transitions. since tw notification precedes tsd, software polling of the tw bit enables avoidance of thermal shutdown. thermal warning and shutdown timing is shown in figure 23. the tw status bit is set when a half?bridge?s sensor temperature exceeds the warning level (t j > twr), and the bit is automatically cleared when sensor temperature falls below the warning hysteresis level (t j < twhy). a channel?s output state is unaffected by tw. when sensor temperature exceeds the shutdown level (t j > tsd), the channel?s hs and ls drivers are latched off, the tw bit is/remains set, and the tsd (pre_15) bit is set. the tsd bit is cleared and all affected channels in a group are re?activated (t j < tsdhy) by sending srr = 1. the channel group select (hbsel) input bit determines which channels are affected by srr. outx on t si status output state so outx on no fault tsd twr t j tw no fault tw no fault no fault outx on tw outx on tw twhy tsdhy outx on srr=1 tsd tw tsd tw tw outx on srr=1 tw outx on tw figure 23. thermal warning and shutdown timing outx z outx on
ncv7719 http://onsemi.com 24 thermal performance estimates 0 10 20 30 40 50 60 70 80 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 figure 24. ja vs. cu area and thickness copper heat spreader area (mm 2 ) ja ( c/w) 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 900 200 180 160 140 120 100 80 60 40 1.0 oz 2.0 oz spreader based on jesd51?3 figure 25. maximum power vs. cu area and thickness copper heat spreader area (mm 2 ) maximum power (w) spreader based on jesd51?3 1.0 oz 2.0 oz r(t) ( c/w) figure 26. transient r(t) vs. area for 2 oz spreader pulse time (sec) 200 mm 2 600 mm 2 spreader based on jesd51?3 ordering information device package shipping ? NCV7719DQR2G ssop24 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv7719 http://onsemi.com 25 package dimensions case 940ak issue o dim min max millimeters a 1.70 a1 0.00 0.10 l 0.40 0.85 e 0.65 bsc c 0.09 0.20 h 0.25 0.50 b 0.19 0.30 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. dambar protrusion shall be 0.10 max. at mmc. dambar cannot be located on the lower radius of the foot. dimension b applies to the flat section of the lead between 0.10 to 0.25 from the lead tip. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension d is determined at datum plane h. 5. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimension e1 is determined at da- tum plane h. 6. datums a and b are determined at datum plane h. 7. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. 8. contours of the thermal pad are un- controlled within the region defined by dimensions d2 and e2. pin 1 reference 0.10 seating plane 24x b e detail a --- soldering footprint* l l2 gauge detail a e1 3.90 bsc plane seating plane c c h end view a-b m 0.12 d c top view side view a-b 0.20 c 112 24 a b d 2x 12 tips a1 a2 c c 24x d 8.64 bsc e 6.00 bsc 24x 1.15 24x 0.40 0.65 dimensions: millimeters pitch 6.40 1 2x a m 13 0.20 c 0.20 c 2x 0.10 c recommended a2 1.65 1.10 e e1 d note 5 note 6 note 6 note 4 a-b m 0.15 d c bottom view e2 note 8 d2 note 8 a-b m 0.15 d c 2.84 5.63 d2 5.28 5.58 e2 2.44 2.64 l1 1.00 ref h a1 note 7 l1 h *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
ncv7719 http://onsemi.com 26 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv7719/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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